The present invention relates to semiconductor fabrication, and in particular to semiconductor devices in which damages to a low-k dielectric layer therein can be reduced or even prevented and methods for forming the same.
Reduction of integrated circuit size has resulted in levels of electrically conductive interconnects being placed closer together vertically, as well as reduction of the horizontal spacing between the electrically conductive interconnects, such as metal lines, on any particular level of such interconnects. As a result, capacitance has increased between such conductive portions, resulting in loss of speed and increased cross-talk. One proposed approach to solve this problem of high capacitance is to replace the conventional silicon oxide (SiO2) dielectric material, having a dielectric constant (k) of about 4.0, with another insulation material having a lower dielectric constant to thereby lower the capacitance.
Unfortunately, low-k dielectric materials have characteristics that make it difficult to integrate into existing integrated circuit structures and processes. Compared to the conventional silicon dioxide (SiO2), the low-k materials, due to the inherent properties thereof, typically have disadvantages such as low mechanical strength, high moisture absorption, poor adhesion, and instable stress level. Thus, replacement of conventional silicon dioxide (SiO2) with low-k dielectric material in integrated circuit processes or structures becomes problematic, resulting in undesirable reliability problems due to physical damage to the low-k materials.
FIGS. 1-4 are cross sections showing fabrication steps of a conventional damascene process for forming interconnects, illustrating occurrence of undesired low-k dielectric damage therein.
In FIG. 1, a silicon substrate having semiconductor devices and/or other existing conductive features is provided with a low-k dielectric layer 10 thereon, with only the low-k dielectric layer 10 illustrated here for simplicity. The low-k dielectric layer 10 comprises low-k dielectric with an inherent dielectric constant less than that of undoped silicon dioxide (about 4.0).
The low-k-dielectric layer 10 is then processed by, for example, a conventional single damascene process to form a plurality of openings op, filled by a bulk copper layer 14 formed thereon. A diffusion barrier layer 12, such as a tantalum nitride (TaN) layer, is conformably formed between the low-k dielectric layer 10 and the bulk copper layer 14 to prevent dopants or metal ions in the bulk copper layer 14 from diffusing into the low-k dielectric layer 10.
In FIG. 2, a first chemical mechanical polishing (CMP) is performed to remove the portion of the bulk copper layer 14 above the diffusion barrier layer 12 and stops on the diffusion barrier layer 12, leaving the copper layer 14a in the openings op.
Next, in FIG. 3, a second CMP is performed to remove the portion of the diffusion barrier layer 12 over the top surface of the low-k dielectric layer 10 and stops on the low-k dielectric layer 10.
Next, in FIG. 4, a third CMP is performed to polish the low-k dielectric layer 10, removing a portion of the low-k dielectric layer 10 to prevent conductive residue of the diffusion barrier layer 12 and/or the bulk conductive layer 14a from remaining on the top surface of the low-k dielectric layer 10, forming a plurality of conductive features S in the low-k dielectric layer 10. Each conductive feature S comprises a diffusion barrier layer 12a and a copper layer 14a which may function as an interconnect, such as contact plug or conductive line.
Due to inherently poor mechanical strength of the low-k material, the low-k dielectric layer 10 is damaged and lowered to a depth d1 of more than 200 Å below the top surface of the remaining copper layer 14a during the described second and third CMP processes, thus forming interconnects with an uneven surface conformation, as shown in FIG. 4. The uneven surface conformation of the formed interconnects makes it undesirable for substantial fabrication processes and may cause reliability problems in completed semiconductor devices.
Semiconductor devices and methods for forming the same in which damages to a low-k dielectric layer therein can be reduced or even prevented are provided. An exemplary method for forming semiconductor devices is provided, comprising providing a dielectric layer with at least one opening therein. A conductive barrier layer is formed over the dielectric layer and the opening. The opening is filled by a conductor over the conductive barrier layer. The exposed portion of the conductive barrier layer is converted into a substantially insulating film.
Another method for forming semiconductor devices is provided, comprising providing a low-k dielectric layer with at least one opening therein. A conductive diffusion barrier layer is conformably formed over the low-k dielectric layer and the opening, wherein the conductive diffusion barrier layer has a thickness less than 10 Å. A conductive layer is formed over the low-k dielectric layer, filling the opening. The portion of the conductive layer above the low-k dielectric layer and the portion of the diffusion barrier over the low-k dielectric layer are removed thereby exposing the top surface of the low-k dielectric layer and forming at least one conductive feature.
In addition, a semiconductor device is provided, comprising a substrate. A low-k dielectric layer with at least one conductive feature therein overlies the substrate. An insulating cap layer overlies the top surface of the low-k dielectric layer adjacent to the conductive feature, wherein the insulating cap layer comprises metal ions.
A detailed description is given in the following embodiments with reference to the accompanying drawings.